ASIP - Thousand Islet Lake

Application Specific Instruction Proccessor

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The performance of an ASIP can be tailored to approach the limits of architecture and technology, offering reduced costs, improved flexibility, and well-established programming environments for developers.

Vector DSP - Sayram Lake

VLIW with 4 instructions issue in parallel

512bits data parallel vector architecture

GCC/ LLVM based toolchain

DSP enhancement instructions including LUT, ZC, cordic, division, interleaving, modulation, and demodulation, etc.

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Network Processor - Tai Lake

DataPlane accelerated processing

Supports ACL and FlowClassifier

Supports L3/L4/L5 packet parsing

Supports hard-accelerated Hash algorithms

Supports DPDK

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Reference Design

5G 4T4R RRU

 

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Reference Design

5G 4T4R dual mode RRU

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Reference Design

5G 2T2R RRU

 

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Blade20 PicoRRU

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Blade22 PicoRRU

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Blade40 PicoRRU

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The world's first 5G base station digital front-end SOC

supporting O-RAN standards

Meri - UC1046 SOC

Digital Front-End Device

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For NR/LTE Micro, Pico and Femto Base Stations

Namjagbarwa - UC6000 Series

Small Cell SoC Platform

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