The performance of an ASIP can be tailored to approach the limits of architecture and technology, offering reduced costs, improved flexibility, and well-established programming environments for developers.
Vector DSP - Sayram Lake
VLIW with 4 instructions issue in parallel
512bits data parallel vector architecture
GCC/ LLVM based toolchain
DSP enhancement instructions including LUT, ZC, cordic, division, interleaving, modulation, and demodulation, etc.
