ASIP - Thousand Islet Lake
The performance of an ASIP can be tailored to approach the limits of architecture and technology, offering reduced costs, improved flexibility, and well-established programming environments for developers.
Technology
Vector DSP - Sayram Lake
• VLIW with 4 instructions issue in parallel
• 512bits data parallel vector architecture
• GCC/ LLVM based toolchain
• DSP enhancement instructions including LUT, ZC, cordic, division, interleaving, modulation, and demodulation, etc.
• Data Plane acceleration, especially ingress and egress processing
• ACL and Flow Classifi er
• eCPRI & CPRI dedicated acceleration
• L3/L4/L5 packet parsing
• Hard-accelerated Hash algorithm
• Data format adaptive
• DPDK
Network Processor - Tai Lake
