Digital Chip and Algorithm Design Engineer

1. Responsible for the baseband physical layer digital front-end module algorithm evaluation, fixed-point and module verification work, participate in the system structure design

2. Cooperate to complete chip-level design verification, FPGA function verification, ASIC synthesis and timing convergence processes

WiFi Design Engineer

1. Responsible for the link construction, performance evaluation and optimization of WIFI physical layer related algorithms

2. Responsible for key algorithm module development, algorithm program evaluation and development work

3. Responsible for the fixed-point algorithm module and guide the hardware to optimize the design of the architecture

4. Assist software and hardware development team to complete algorithm implementation and verification

5. Responsible for the follow-up analysis of relevant standards and algorithm pre-research work

WiFi physical layer and MAC layer

Algorithm Design Engineer

1. Microelectronics, communications and other related professional graduate, software engineer

2. Familiar with WiFi AP physical layer algorithm and working process, familiar with WiFi MAC layer protocol

3. Proficient in C language or MATLAB language. Working experience, master's degree is preferred, with small team experience is preferred

Flow Engineer

1. Responsible for the front-end process of SoC chip, including sdc file, UPF file, synthesis, formal verification, etc. (module level and chip level)

2. Responsible for SoC chip low power flow

3. Responsible for communication and cooperation with back-end engineers, responsible for chip STA analysis, and assisting in timing convergence

4. Responsible for DFT test scheme design and DFT implementation, vector generation and problem debug of ATE test

Digital Back-End Engineer

1. Be responsible for the back-end module development of SoC chips, including layout and routing, clock tree analysis, etc.

2. Be responsible for module-level power analysis of SoC chips

3. Be responsible for chip STA analysis and complete timing convergence

4. Able to complete chip physical verification

ASIC Verification Engineer

1. Responsible for SoC chip module-level, system-level verification, complete verification coverage analysis and verification documentation

2. Cooperate to complete chip-level verification and FPGA functional verification

ASIC Design Engineer

1. Responsible for module-level architecture design, code design and verification of SoC chips, complete design and verification documentation

2. Cooperate to complete chip-level design verification, FPGA function verification, ASIC synthesis and timing convergence processes

AE Engineer

1. Be responsible for the selection of electronic components and the schematic/layout of PCB, select PCB production and welding manufacturers, and ensure the timely and quality release of PCB

2. Responsible for the management and maintenance of laboratory devices, circuit boards and equipment

3. Assist designers to complete commissioning and testing, maintain project testing and quality management documents

DFT Engineer

1. Complete the design and verification of chip modules and top-level DFT, including MBIST, SCAN,Boundary scan, etc.

2. Generate ATPG and verify ATPG test vector, and participate in ATE test and problem location

3. Assist the back-end team to handle DFT-related timing analysis and timing convergence

4. Responsible for the design of DFT system integration scheme 5. Responsible for the improvement of DFT process

Vector Processor Toolchain Designer

Responsible for vector processor compiler assembler design and tool chain integration

SoC multi-core virtual machine development/multi-core heterogeneous programming development designer

Responsible for vector processor compiler assembler design and tool chain integration